High speed tristate bus with multiplexers for selecting bus driver

ABSTRACT

According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of multiplexers is connected into a chain. The tristate enable line of the tristate buffer becomes the control line for enabling the multiplexer to place its own input signal into the chain instead of propagating the signal already in the chain. A buffer element then drives the resulting signal onto an output line of the chain. One embodiment of the invention includes lookahead logic similar to a lookahead carry chain. This allows large numbers of input lines to be connected to a bus line while retaining high speed. An embodiment implements the lookahead feature using AND gates and OR gates and thereby further increases speed and reduces size.

FIELD OF THE INVENTION

The invention relates to programmable integrated circuit devices,particularly FPGAs, and to controlling input signals for driving a bus.

BACKGROUND OF THE INVENTION

The overall structure of an FPGA is described by Freeman in U.S. Pat.No. Re. 34,363. An FPGA includes configurable logic blocks and aconfigurable interconnect structure for connecting the logic blocks andotherwise routing signals through the FPGA. An FPGA may be configured toperform a particular function by turning on and off particulartransistors in the FPGA to select functions performed by the logicblocks of the FPGA and to connect the logic blocks to each other throughinterconnect lines. One FPGA architecture with which the presentinvention will work is described by Tavana et al in U.S. patentapplication Ser. No. 08/222,138 M-2257-1N! entitled FPGA Architecturewith Repeatable Tiles Including Routing Matrices and Logic Matrices. Thesubject matter of this patent application is incorporated herein byreference.

It is common to use a single bus line for alternatively providing one ofseveral signals to a circuit element. When a bus line is used, a controlsystem must assure that only one driver uses the bus at one time. (A busline may alternatively be used to provide a signal from a single source,or may be used to generate a wired-AND function by connecting a pull-upresistor and many pull-down signal sources of which none or many may beconnected simultaneously.) FPGA integrated circuit chips having atristate buffer structure for alternately placing multiple signals ontoone bus line are available in the XC4000 and XC5200 families of devicesavailable from Xilinx, Inc., assignee of the present invention. Thetristate buffer feature of the Xilinx XC4000 family of products isdescribed in the Xilinx 1994 Data Book at pages 2-16 and 2-24. TheXC5200 family is illustrated in the XC5200 Logic Cell Array FamilyTechnical Data published Oct. 1995, pages 1-20. The tristate buffer isillustrated at pages 5 and 11.

In the Xilinx XC4000 and XC5200 families of FPGA devices, certain of theinterconnect lines can serve as bus lines. Output terminals of severaltristate buffers are connected to these lines and a control structure ispresent in the FPGA for selecting which tristate buffer places itssignal onto the interconnect line.

FIG. 1 shows a tristate buffer structure including two line segments O1and O2 which may or may not be connected together using programmableconnector C2 to form a single bus line, and eight tristate buffers B1through B8 for alternatively driving the line segments. Each buffer B1through B8 typically receives an input signal from a differentconfigurable logic block of the FPGA. (These configurable logic blocksare not shown in FIG. 1.) The bus line segments O1 and O2 can also beconnected to terminals of configurable logic blocks via localinterconnect line segments. FIG. 1 shows two configurable logic blocks,CLB1 and CLB2, which can be programmably connected to line segments O1and O2 respectively. Programmable connectors such as C1, C1a, C1b, C1c,and C3 make these connections. Also, programmable connector C2 connectsline segments O1 and O2 together. A control system, not shown, places anenable signal (may be active high or active low) on a selected tristateenable line E1 through E8 and thereby connects the selected input lineI1 through I8 to its corresponding bus line segment O1 or 02. Ifprogrammable connector C2 is not connecting segments O1 and O2 together,each segment may receive its own driving signal.

FIG. 2 shows symbols used in the drawings, including a small black dotto indicate a permanent connection, a white circle to indicate aprogrammable connection not connected, and a black circle to indicate aprogrammable connection that is connected.

FIG. 3 shows part of a logic design which a user may wish to implementin an FPGA. In this example, the design has seven signals S1 through S7to be alternatively placed onto a bus BUS1, which provides an inputsignal to a logic unit L1. Software is available to receive a user'sdesign, including a structure such as illustrated in FIG. 3, and toselect components of an FPGA which will implement each portion of thedesign. This software typically partitions the user's design intoportions which will be implemented in a CLB and its related tristatebuffers (called partitioning or mapping), then selects particular CLBsand tristate buffers to implement each portion (called placement), andfinally selects interconnect lines to connect the pieces togetheraccording to the user's design (called routing). Sometimes, because ofother logic not shown in FIG. 3, the placement step may choose to skip atristate buffer when placing the logic for generating signals S1 throughS7.

FIG. 4 shows an example implementation of the user's design of FIG. 3 inthe FPGA structure of FIG. 1. In order to alternatively connect sevensignal lines to the same bus, segments O1 and O2 are connected togetherby turning on connector C2. The user's logic represented in FIG. 3 by L1is implemented in FIG. 4 by CLB1. Thus connectors C1 and C1b are turnedon to connect segment O1 to CLB1. Connector C3 is not turned on, sinceCLB2 is not used to implement the design of FIG. 3. Because of placementand possible other considerations, the signal S7 of FIG. 3 will begenerated in a non-contiguous logic block and placed onto signal lineS8. Thus, buffer B7 is disabled by connecting enable line E7 to groundthrough connector C4. During operation, the control structure (notshown) places a high signal onto one of E1 through E6 and E8 to turn onone of the corresponding buffers B1 through B6 and B8. The selectedsignal S1 through S7 placed on line I1 through I6 and I8 is thenprovided to CLB1.

The structure of FIGS. 1 and 4 requires that each of buffers B1 throughB8 be of sufficient size to drive any other circuit elements that may beconnected to bus lines O1 and 02. If many input signals may be bufferedonto the bus and many circuit elements may be driven by the bus, thesize of the structure of FIG. 1 can be undesirably large or else thespeed of signal propagation can be undesirably slow.

SUMMARY OF THE INVENTION

According to the invention, a structure is provided for driving a busline that is both fast and small. Instead of a plurality of tristatebuffers, one for each input signal, a plurality of multiplexers isconnected into a chain. The tristate enable line of the tristate bufferbecomes the control line for enabling the multiplexer to place its owninput signal into the chain instead of propagating the signal already inthe chain. A buffer element then drives the resulting signal onto anoutput line of the chain.

One embodiment of the invention includes lookahead logic similar to alookahead carry chain. This allows large numbers of input lines to beconnected to a bus line while retaining high speed. An embodimentimplements the lookahead feature using AND gates and OR gates andthereby further increases speed and reduces size.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art tristate buffer structure for driving a bus.

FIG. 2 shows symbols used in the drawings.

FIG. 3 shows part of a logic design which a user may wish to implementin an FPGA.

FIG. 4 shows an example implementation of the user's design of FIG. 3 inthe prior art FPGA structure of FIG. 1.

FIG. 5 shows a bus structure according to the invention.

FIG. 6 shows a structure with a lookahead circuit for shortening thedelay of the multiplexer chain.

FIG. 7 shows how the circuit of FIG. 6 can be simplified without anyloss of function.

FIG. 8 shows a further simplification from FIG. 7.

FIG. 9 represents part of a user's design.

FIG. 10 shows how the structure of FIG. 8 will implement the design ofFIG. 9.

FIG. 11 illustrates part of another design.

FIGS. 12 and 13 illustrate two ways the design portion of FIG. 11 can beimplemented.

FIG. 14 shows another embodiment similar to FIG. 8.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 5 shows a bus structure according to the invention implementedwithin a FPGA structure. Shaded regions indicate the interconnectstructure of the FPGA. In a commercial device, many more programmableconnections than those shown are available. In order to avoid clutteringthe drawing, only a minimum number have been shown. Illustrated betweenthe interconnect regions are logic units in which are positionedconfigurable logic blocks labeled CLB. The bus structure makes use ofboth lines in the general interconnect and multiplexers in the logicunits. A first multiplexer chain comprises multiplexers 50a-54a andbuffer 55a. A second chain comprises multiplexers 50b-54b and buffer55b. Multiplexer 50a can receive an input signal on line 46 from anotherchain to the left, not shown, or can receive a signal on line 47a fromthe general interconnect structure. For starting a chain, a groundsignal can also be applied to line 47a. Multiplexer 50a is controlled bya memory cell 49a. A logic 1 in memory cell 49a causes the signal online 47a to be forwarded to multiplexer 51a. A logic 0 in memory cell49a causes the chain to continue from line 46. If no enable signal online E1 through E4 is a logic 1, then the output signal from multiplexer50a is forwarded to buffer 55a and placed onto bus line 56a. If anyenable signal on line E1 through E4 is logic 1, then the signal on thecorresponding multiplexer input line I1 through I4 is placed onto bus56a. There should be only one logic 1 enable signal among all enablesignals for driving one bus. If this is the case, then the multiplexerchain will forward the input signal associated with that logic 1 to theoutput bus. If, through a design error or other reason, more than oneenable signal is high, there will be no signal contention, in contrastto the prior art tristate buffer structure. The rightmost signal will beapplied to the output bus line 56a. No damage will be done to the chipby this action, in contrast to the prior art structure of tristatebuffers.

In any sequence of chains comprising a bus line, the first chain will beinitialized to logic 0, for example via connector 48a. Thus, if none ofthe enable signals E1 through E4 is high, the logic 0 will propagatethrough the chain and the output will be logic 0. The second chain canbe connected to the first chain by placing logic 0 into memory cell 49b.This allows eight input signals to drive a single output bus line 56b.An actual FPGA will typically include many adjacent units with the samestructure. Thus a very large number of input signals can bealternatively selected to drive one bus line. And many separate busescan be constructed from these adjacent units. Also, using input line 47(47a, 47b, for example), allows an output signal on a bus line 56 (56a,56b, for example) to be connected to a non-adjacent chain. Thus multiplenon-adjacent chains can be joined to form one bus line.

With the structure of FIG. 5, the delay caused by a long chain ofmultiplexers may be undesirably large. FIG. 6 shows an FPGA with alookahead structure for shortening the delay of the multiplexer chain.Two parallel chains of multiplexers 61-64 and 71-74 receive leading 1and 0 respectively and provide their respective output signals to themultiplexer to the right, eventually to multiplexer 65. If the output ofmultiplexer 60a is 1, the chain with the leading 1 (1-chain) isselected, that is, the output of multiplexer 64 is selected bymultiplexer 65. If the output of multiplexer 60a is 0, the 0-chain isselected, that is, the output of multiplexer 74 is selected. Thestructure of FIG. 6 allows the output of multiplexer 60 to controlmultiplexer 65 without encountering the signal path delay of FIG. 5.

FIG. 7 shows how the circuit of FIG. 6 can be simplified without anyloss of function. In FIG. 6, if any of signals I1 through I4 is to beplaced onto the bus, its enable line E1 through E4 will be high. Thefunctionality of a tristate bus line requires that the design cause allother enable signals to be inactive, and thus the logic 0 whichinitiated the chain is propagated to multiplexer 60a. Thus, the outputfrom multiplexer 60a should be logic 0, causing the 0-chain to beselected by multiplexer 65a. Only if a logic 1 is being propagated fromthe left will multiplexer 60a cause multiplexer 65a to select the1-chain. And when the 1-chain is selected, this means that a multiplexerto the left was enabled and its input signal was logic 1. This requiresthat all enable signals E1 through E4 be inactive. So whenever the1-chain is selected, the constant logic 1 input signal will propagate tomultiplexer 65a. Thus the 1-chain is not needed. In FIG. 7, the 1-chaincomprising multiplexers 61a-64a is eliminated and the memory cellinitiating the 1-chain becomes a direct input to multiplexer 65a.

Memory cells can be used to load the 0 or 1 into the input ofmultiplexer 71a and multiplexer 65a, and therefore these structures areprogrammable. Thus, the structure illustrated in FIG. 7 can be used forother functions than a tristate buffer, in particular to generate ANDand 0R functions, by loading different values into the inputs ofmultiplexers 71a and 65a.

FIG. 8 shows a further simplification from FIG. 7. A multiplexer with aconstant 0 input can be replaced by an AND gate. Thus AND gate 81a ofFIG. 8 replaces multiplexer 71a and the leading 0 memory cell of FIG. 7.A multiplexer with a constant 1 input can be replaced by an OR gate.Thus multiplexer 65a and the logic 1 memory cell are replaced by OR gate85a. Because an OR gate provides a buffered output signal, buffer 66a ofFIG. 7 can also be eliminated. A signal starting to the left of line 46and propagating to a point to the right of bus line 56b is delayed onlyby the pass transistor in multiplexer 60a, the drive transistor in ORgate 85a, the pass transistor in multiplexer 60b and the drivetransistor in OR gate 85b. Thus the path is faster than that of FIG. 5.

FIGS. 9-13 show examples of how the structure of FIG. 8 can implementsome designs.

FIG. 9 represents part of a user's design, namely two logic devices, L1and L2, each of which can alternately receive one of several inputsignals. Logic device L1 is to receive one of input signals S1 throughS4 and logic device L2 is to receive one of input signals S5 through S7.The user has indicated that the signal for logic device L1 will beplaced onto bus BUS1 and the signal for logic device L2 will be placedonto bus BUS2. Selection of signals S1 through S7 is to be controlled bytristate control signals T1 through T7, respectively.

FIG. 10 shows how the structure of FIG. 8 will implement the design ofFIG. 9. Memory cell 49a is loaded with a logic 1 and a ground signal isapplied to line 47a through connector 48a. This causes multiplexer 60ato forward the ground signal to OR gate 85a and thus causes OR gate 85ato respond to the multiplexer chain comprising AND gate 81a andmultiplexers 72a through 74a. Bus line 56a is connected to the generalinterconnect structure at connector C12. Interconnections not shown formthe path illustrated in dashed lines from connector C12 to connectorC13. Connector C13 connects the interconnect structure to configurablelogic block CLB1, which is configured to implement logic L1. Signals S1through S4 are applied to lines I1 through I4 and tristate controlsignals T1 through T4 are applied to enable lines E1 through E4. Thisimplements the left portion of FIG. 9.

To implement the right portion of FIG. 9, a logic 1 is loaded intomemory cell 49b so that bus line 56a will not be connected to OR gate85b. A ground signal is applied through connector 48b and multiplexer60b to 0R gate 85b so that OR gate 85b will respond to the multiplexerchain comprising AND gate 81b and multiplexers 72b, 73b, and 74b. Aground signal is applied to enable line E7 of multiplexer 73b throughconnector C21 so that input line I7 will be ignored and the signal frommultiplexer 72b will be passed to multiplexer 74b. (This assumes thesoftware has decided that the logic illustrated in FIG. 9 fits betterwith the total logic placement when multiplexer 73b is skipped.)Connections are made at C14 and C15, thus applying the output of OR gate85b to configurable logic block CLB2, which is programmed to implementlogic L2. Signals S5 and S6 are applied to I5 and I6. Signal S7 isapplied to input line I8. Tristate control signals T5 and T6 are appliedto enable lines E5 and E6. Tristate control signal T7 is applied toenable line E8. Thus the configuration of FIG. 10 implements the logicdesign portions shown in FIG. 9.

FIG. 11 illustrates part of another design. FIGS. 12 and 13 illustratetwo ways this design portion can be implemented. The design of FIG. 11selects from seven input signals S1 through S7, and provides theselected signal to both of logic elements L3 and L4.

In FIG. 12, connector C12 is not used to connect line 56a to theinterconnect structure. The left portion of the structure is configuredas in FIG. 10. On the right, memory cell 49b is loaded with a logic 0 sothat the output signal from OR gate 85a is applied to OR gate 85b. As inFIG. 10, multiplexer 73b is bypassed. The output of OR gate 85b isapplied to the interconnect structure by turning on connector C14. Apath is formed through the interconnect structure and through connectorsC13 and C15 to configurable logic blocks CLB1 and CLB2, which implementlogic portions L3 and L4.

Note that OR gate 85b will provide a logic 1 output signal if the inputsignal S1 through S7 is high when the corresponding tristate enablesignal T1 through T7 is high. Or gate 85b will provide a logic 0 outputsignal if the input signal S1 through S7 is low when the correspondingtristate enable signal T1 through T7 is high. If no enable signal ishigh, OR gate 85B will provide a logic 0 output signal.

FIG. 13 illustrates an alternative implementation of the same logic, andillustrates that the input signals for driving a bus need not be placedalong the same line. Signals S1 through S4 are placed on lines I1through I4, as before. However, signals S5 through S7 have been placedonto lines I10 through I12 in another row.

As before, connector C12 connects line 56a to the general interconnect.A path is found through the general interconnect from connector C12 toconnector C18, to provide the output signal from OR gate 85a to line47c, which is on another row and another column. Memory cell 49c isloaded with a logic 1 to forward the signal to OR gate 85c. Enable lineE9 is connected to ground through connector C21, so input line I9 isignored. Signals S5 through S7 are placed onto lines I10 through I12 andtristate control signals T5 through T7 are placed onto enable lines El0through El2. Connector C19 places the output of OR gate 85c onto thegeneral interconnect structure. Connectors C16 and C17 forward thesignal from the general interconnect structure to CLB3 and CLB4. CLB3will implement logic L3 and CLB4 will implement logic L4. As the signaltravels through the interconnect structure it may be buffered as needed.Thus a bus line can be formed using general interconnect line segmentsin combination with the fast lines such as 56a for connecting adjacentsegments. This increases the flexibility of the FPGA for placing largedesigns compactly into the FPGA.

It is clear from the above description that the present invention allowsa bus line to be formed from a combination of interconnect lines whichdo not have to be in a particular relationship to each other. From thesimple examples shown, one of ordinary skill in the art will understandhow to implement many other designs in many arrangements. For example,in FIG. 8, AND gate 81 at the beginning of a chain and OR gate 85 at theend of a chain can alternatively be implemented as an OR gate at thebeginning and an AND gate at the end of a chain as shown in FIG. 14. Ofcourse, the ground signal at connector 48a of FIG. 8 must be replaced bya Vcc signal at connector 98a in order to cause AND gate 95a to pass themultiplexer chain signal. Also, even though the illustration groupsinput lines into sets of four, another number may be chosen. Suchalternative embodiments are intended to fall within the scope of thepresent invention.

We claim:
 1. A plurality of multiplexer chains each comprising:aplurality of multiplexers connected into a chain with an output terminalof one multiplexer being connected to an input terminal of a nextmultiplexer and an input signal being connected to an input terminal ofeach multiplexer, each multiplexer being controlled by a tristate enablesignal on a multiplexer control terminal; means for connecting to eachchain a signal derived from an FPGA interconnect structure; means forconnecting an output signal of each chain to said FPGA interconnectstructure.
 2. A plurality of multiplexer chains as in claim 1 in whichsaid means for connecting an output signal of each chain to said FPGAinterconnect structure comprises means for selecting between connectingto said FPGA interconnect structure an output terminal of said eachchain and an output terminal of another chain in an adjacent position.3. A plurality of multiplexer chains as in claim 2 in which said eachchain is initialized with a constant value.
 4. A plurality ofmultiplexer chains as in claim 3 in which said constant value isprovided by implementing a first multiplexer as an AND gate and saidmeans for connecting an output terminal of each chain to the outputterminal of another chain in an adjacent position comprises an OR gate.5. A plurality of multiplexer chains as in claim 3 in which saidconstant value is provided by implementing a first multiplexer as an ORgate and said means for connecting an output terminal of each chain tothe output terminal of another chain in an adjacent position comprisesan AND gate.
 6. A plurality of multiplexer chains as in claim 1 in whichsaid signal derived from said FPGA interconnect structure is connectedto an input terminal of a first multiplexer in each chain.
 7. Aplurality of multiplexer chains as in claim 1 in which said signalderived from said FPGA interconnect structure is multiplexed with anoutput signal from a last multiplexer in each chain.